| 1 |
Introduction |
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| 2 |
Hierarchical Modelling, Test and Simulation |
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| 3 |
Verilog Basic Concepts |
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| 4 |
Modules and Ports |
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| 5 |
Gate-level Modelling |
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| 6 |
Dataflow Modelling |
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| 7 |
Synthesis |
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| 8 |
Programmable ICs |
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| 9 |
Practical Exam (Second Attempt) |
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| 10 |
Static Timing Analysis (Part One) |
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| 11 |
Static Timing Analysis (Part Two) |
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| 12 |
ASIC Design Flow |
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| 13 |
Design Techniques (Performance, Power and Energy Consumption) |
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| 14 |
Behavioral Modelling |
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| 15 |
Tasks and Functions |
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| 16 |
Finite State Machine |
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| 17 |
Practical Exam (First Attempt) |
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| 18 |
Practical Exam (Final Attempt) |
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| 19 |
Introduction to Vivado |
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| 20 |
Project - Part 1 |
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| 21 |
Project - Part 2 |
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| 22 |
Introduction to SystemVerilog |
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| 23 |
Power Analysis Attacks |
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